A typical integrated circuit package comprises a package substrate, a first array of connectors on an exterior surface of the substrate, a second array of connectors on an interior surface of the substrate substantially parallel to the exterior surface and an integrated circuit mounted on the second array of connectors. The connectors of each array are solder balls or solder bumps and will be referred to collectively hereafter as “pins.”
The package substrate is a multi-layer structure comprising a series of electrically conducting metal layers that are insulated from one another by inter-metallic dielectric layers. Each of the layers is substantially parallel to the exterior surface of the package. Interconnection paths are defined in the metal layers; and selective connections are made by vias between the paths in the various layers so as to connect the pins of the first array to the pins of the second array. Further details on package substrates are found in R. R. Tummala (Ed.), Fundamentals of Microsystems Packaging (McGraw-Hill 2001), which is incorporated herein by reference.
As is known in the art, a conventional integrated circuit comprises a semiconductor substrate, such as silicon, in which various devices are formed and a series of metal interconnect layers separated by insulating dielectric layers that overlie the semiconductor substrate. Further details concerning integrated circuits are set forth in N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective (3rd Ed., Pearson Addison Wesley, 2005), which is incorporated herein by reference.
When circuits are switched, noise is generated in the power distribution network. One approach to suppressing this noise is to provide decoupling capacitors in the power distribution network, either in the metal layers of the integrated circuit or in discrete capacitors mounted on the package substrate. Further details on such use of decoupling capacitors are found at pages 169-172 of R. R. Tummala, op. cit., which are incorporated by reference herein.
One application of integrated circuits is as high speed serial interfaces such as those that are compliant with the high speed serial interface (HSSI) protocol. The design of power distribution networks for HSSI circuitry is very complicated; and present networks leave much to be desired. One such design provides a single path power distribution network from a power supply pin on the exterior of the package substrate, through the substrate to a load and a decoupling capacitor on the integrated circuit. A second design provides a three path power distribution network, one path from the power supply pin to a decoupling capacitor on the substrate, a second path from the power supply pin to a decoupling capacitor and load on the integrated circuit, and a third path between the decoupling capacitor on the substrate and the decoupling capacitor on the integrated circuit. Neither design is wholly satisfactory. As shown in FIG. 1, which is a plot of system level impedance versus operating frequency for these networks, the impedance of these networks varies considerably over an operating range of approximately 0 to 600 MHz. Moreover, the single path power distribution network shown as plot 110 has a very high impedance peak; and while the three path power distribution network shown as plot 120 lowers the maximum impedance peak, it increases the impedance over that of the one path network in the region B of approximately 200 to 350 MHz.
In addition, neither the single path nor the three path network design takes into consideration the effect of power noise on signal jitter. For extremely high frequency applications, this effect is largely unknown at the time the circuit is designed. However, this effect can be considerable and must be accounted for.